The present invention is directed to an apparatus wherein input signals are compared or sorted with the assistance of a number of comparator circuits.
A possibility for a place-by-place comparison of two input words is known from the textbook by L. Borucki, Digitaltechnik, 1996, ISBN 3-519-36415-8, Chapter 10, pages 198 and 199.
The rank of more than two input signals is usually determined with a cascade-like structure of comparators, whereby each comparator makes the decision for two input quantities and respectively hands the highest input value over to the next comparator stage until the last comparator stage ultimately determines the highest input signal. When, over and above this, even more next-higher values are required, then the highest values that have already been determined can be correspondingly excluded for a further search. Given such a simple sorting means, the processing time is proportional to the number M of input signals, which is especially disadvantageous particularly given high values of M.
An object of the present invention is to provide an apparatus that, given comparable circuit outlay, allows a higher processing speed, particularly given large numbers of inputs.
This object is inventively achieved in an embodiment of an apparatus for a fast determination of a prescribable number of highest value input signals from a number of input signals each comprising an input word having a number of recoders, each one of the recoders having an input for receiving one of the input signals. The recoders recode the input words into expanded input words having significant bits dependent on a value of the input words and have an output for outputting the expanded input words. A sorting logic has a first input for receiving a control signal identifying the prescribable number and a second input for receiving the expanded input words. The sorting logic forms and outputs a prescribable number of output words of highest value input signals from the expanded input words.
In an embodiment, the sorting logic further comprises an adder module for concurrently receiving bits of the expanded input words, being ordered according to their place value, from the recorders, and outputting sum signals at an output. A comparator module connected to the output of the adder module compares the sum signals to the prescribable number and has an output. A switch module is driven by the comparator output connected to a first input of the switch module. The switch module has a second input for concurrently receiving the bits of the expanded input words, being ordered according to their place value, and an output for passing through the bits of the expanded input words selectively determined by the comparator output. An encoder module has an input connected to the output of the switch module and forms and outputs the prescribable number of output words of highest value input signals from the expanded input words being passed through from the switch module.
In an embodiment, the number of input signals further comprises M input signals. The expanded input words further comprise a word width k, wherein the adder module further comprises M*kxe2x88x921 adder modules, an ith adder module of the M*kxe2x88x921 adder modules further compring ixe2x88x921 inputs, with i being an integer defined 1 less than i less than M*kxe2x88x921. A most significant bit of a first expanded input word is directly inputted to the comparator module. And, the bits of the expanded input words, being ordered according to their place value, are sequentially received at the ith adders.
These and other features of the invention(s) will become clearer with reference to the following detailed description of the presently preferred embodiments and accompanied drawings.